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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
GENERAL DESCRIPTION
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EM73P968 is an advanced single chip CMOS 4-bit one time programming (OTP) micro-controller. It contains 16K-byte ROM, 2.5K nibbles RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/ counters for the kernel function. EM73P968 also contains 6 interrupt sources, 1 input port, 8 bidirection ports, Max LCD display (52x5), built-in watch-dog-timer and high speed Timer/Counter. An analog to digital (A/D) converter having 8-bit multipler analog input and 8-bit resolution. Serial peripheral interface (SPI). EM73P968 has plentiful operating modes (SLOW, IDLE, STOP) intended to reduce the power consumption.
FEATURES
Operation voltage Clock source : 2.2V ~ 6V. : Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32K Hz, connect an external resistor) by mask option and high-frequency oscillator is RC (Connect an external resistor) or Crystall oscillator. Instruction set : 107 powerful instructions. Instruction cycle time : Up to 2us for 4 MHz (high speed clock). 122 s for 32768 Hz (low speed clock with frequency Double) ROM capacity : 16K x 8 bits. RAM capacity : 2.5K x 4 bits. Input port : 1 port, P0(0..3), IDLE/STOP releasing function are available by mask option. Output port : 9 pins (P17.0, P30, P31), P17.0, P30, P31 are shared with LCD pins. Bidirection port : 9 ports (P1, P2, P4, P5, P6, P7, P8, P11, P15). IDLE/STOP releasing function are available by mask option for P8(0..3), P5 and P6 have high current sink. 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement. A/D converter : An analog to digital (A/D) converter having 8-bit multipler analog input and 8-bit resolution. SPI : Serial peripheral interface. Built-in watch-dog-timer : It is available by mask option. Built-in time base counter : 22 stages. Built-in high Speed Timer/Counter : Could be timer. Subrountine nesting : Up to 13 levels. Interrupt : External . . . . . 2 input interrupt sources. Internal . . . . . . 2 Timer overflow interrupts, 1 time base interrupt. 1 high speed counter overflow interrupt. LCD driver : 52 X 5 dots, 1/3 bias, 1/4 or 1/5 duty by mask option. Power saving function : SLOW, IDLE, STOP operation mode. Package type : Chip form. QFP 128 pin.
APPLICATIONS
EM73P968 is suitable for application in family applicance, consumer products, hand held games, calculator and the toy controller.
* This specification are subject to be changed without notice.
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FUNCTION BLOCK DIAGRAM
VDD RESET XOUT XIN
inary Prelim
LXOUT LXIN
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SPI Reset Control Clock Generator Clock Generator (slow) System Control Data pointer Interrupt Control Time Base TEST V1 V2 V3 VRLC Instruction Decoder Instruction Register ACC Stack pointer Stack RAM S HR PC I/O Control LCD ADC LR Timing Generator Sleep Mode Control
P15.0/P15.1/ WAKEUP
Data Bus
ALU Flag Z C
Timer/Counter (TA,TB)
ROM
P0/WAKEUP P2 /WAKEUP P4 /WAKEUP P5 /WAKEUP
VADSS VAD Vref (AIN 0~3)P6/WAKEUP (AIN 4~7)P7/WAKEUP
COM0~COM3
SEG0~SEG43
P1/WAKEUP
P11/WAKEUP
P15.2/WAKEUP
P15.3/WAKEUP
P30/SEG(44~47)
PIN DESCRIPTIONS
Symbol VDD VSS Vref VAD V ADSS RESET Pin-type Function Power supply (+) Power supply (-) ADC power (+) ADC power (+) ADC power (-) RESET-A System reset input signal, low active mask option : none pull-up XIN/RCOSC OSC-A/OSC-H1 Crystal/RC clock source connecting pin XOUT OSC-A Crystal connecting pin LXIN OSC-B/OSC-H2 Crystal/RC connecting pin for low speed clock source LXOUT OSC-B Crystal connecting pin for low speed clock source P0(0..3)/WAKEUP(0..3) INPUT-K 4-bit input port with IDLE/STOP releasing function P0.0/ACLK : address counter clock for programming OTP. P0.1/PGMB : program data to OTP cells for programming OTP. P0.2/OEB : data output enable for programming OTP. P0.3/DCLK : data in/out clock signal for programming OTP. mask option 1 : wakeup disable wakeup enable mask option 2 :low current pull up normal current pull up high current pull up none 8.14.2001
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* This specification are subject to be changed without notice.
P31/SEG(48~51)
P8/WAKEUP
P17.0/COM4
VSS
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PIN DESCRIPTIONS
Symbol
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Pin-type Function 2-bit bidirection I/O port with external interrupt sources input and IDLE/ STOP releasing function P8.0/DIN : data input for programming OTP mask option 1 : wakeup disable wakeup enable mask option 2 : low current push pull normal current push pull high current push pull none 2-bit bidirection I/O port with timer/counter A, B external input and IDLE/STOP releasing function P8.1/DOUT : data output for programming OTP mask option 1 : wakeup disable wakeup enable mask option 2 : low current push pull normal current push pull high current push pull none 8-bit bidirection I/O port with IDLE/STOP releasing function. Share with A/D analog input pin. mask option 1 : wakeup disable wakeup enable mask option 2 : low current push pull normal current push pull high current push pull none 4-bit bidirection I/O port with IDLE/STOP releasing function mask option 1 : wakeup disable wakeup enable mask option 2 : low current push pull normal current push pull high current push pull none
P8.0(INT1)/WAKEUPA I/O-R1 /DIN P8.2(INT0)/WAKEUPC
P8.1(TRGB)/WAKEUPB, I/O-R1 /DOUT P8.3(TRGA)/WAKEUPD
P6(0..3)/WAKEUP(20..23) I/O-R1 AIN (0..3) P7(0..3)/WAKEUP(24..27) AIN (4..7)
P4(0..3)/WAKEUP(12,15) I/O-R1
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PIN DESCRIPTIONS
Symbol Pin-type P1(0..3)/WAKEUP(4..7) I/O-R1 P2(0..3)/WAKEUP(8..11) P5(0..3)/WAKEUP(16..19) P11(0..3)/ WAKEUP(28..31) P15.2/P15.3/ WAKEUP(34,35) P15.0/WAKEUP(32)
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
P15.1/WAKEUP(33)
I/O-R1
P17.0/COM4
Output-L
P30(0..3)/SEG(51..48) P31(0..3)/SEG(47..44)
Output-M
COM0~COM3 SEG0~SEG43 VRLC, V1, V2, V3 TEST
---
Function 18-bit bidirection I/O pins with IDLE/STOP releasing function mask option 1 : wakeup disable wakeup enable mask option 2 : low current push pull normal current push pull high current push pull none 1-bit bidirection I/O pins with IDLE/STOP releasing function. Share with SPI data input/output pin. mask option 1 : wakeup disable wakeup enable mask option 2 : low current push pull normal current push pull high current push pull none 1-bit bidirection I/O pins with IDLE/STOP releasing function.Share with SPI clock input/output pin. mask option 1 : wakeup disable wakeup enable mask option 2 : low current push pull normal current push pull high current push pull none 1-bit output pin with LCD common pin mask option : LCD common pin Push pull Open-drain 8-bit output pins are shared with LCD segment pin mask option : LCD segment pin Low current push pull Normal current push pull High current push pull Open drain LCD common output pins LCD segment output pins LCD bias voltage pins Test pin must be connected to VSS VPP : high voltage (12V) power source for programming OTP
* This specification are subject to be changed without notice.
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PIN ASSIGNMENT
SEG23 NC NC NC NC NC NC NC SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 VPP ACLK/P0.0 PGM/P0.1 OE/P0.2 DCLK/P0.3 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 RESET P6.0 P6.1 P6.2 P6.3 P7.0 P7.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM4 COM3 COM2 COM1 COM0 P15.3 P15.2 P15.1 P15.0 P11.3 P11.2 P11.1 P11.0 VRLC VR3
inary Prelim
EM73P968
QFP 128
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 NC NC NC NC NC NC NC VR2 VR1 LXOUT VDDC LXIN VSS XOUT VDDI XIN VSS P8.3 P8.2 DOUT/P8.1 DIN/P8.0 VAD VREF VADSS P7.3 P7.2
inary Prelim
FUNCTION DESCRIPTIONS
PROGRAM ROM ( 16K X 8 bits )
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
16 K x 8 bits program ROM contains user's program and some fixed data. The basic structure of the program ROM may be categorized into 5 partitions. 1. Address 0000h : Reset start address. 2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses. 3. Address 000Eh - 0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh, 0086h. 4. Address 0000h - 07FFh : LCALL subroutine entry address. 5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and data region. address Bank 0 :
0000h 0002h 0004h 0006h 0008h 000Ah 000Ch 000Eh 0086h Reset start address INT0 ; interrupt service routine entry address HTCI / ADI TRGA TRGB TBI INT1 SCALL, subroutine call entry address
Subroutine call entry address designated by [LCALL a] instruction
. . .
07FFh 0800h 0FFFh 1000h
1FFFh
Bank 1 Bank 2 Bank 3
Data table for [LDAX],[LDAXI] instruction
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ary elimin Pr User's program and fixed data are stored in the program ROM. User's program is executed using the PC value
to fetch an instruction code. The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits per bank. The program ROM bank is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC and P3 are initialized to "0" during reset. When P3(1..0)=00B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the bank0 and bank2 will be selected. P3=xx00B Address P3=xx11B P3=xx01B P3=xx10B 0000h : : Bank0 Bank0 Bank0 0FFFh 1000h : : Bank1 Bank2 Bank3 1FFFh PROGRAM EXAMPLE:
BANK 0 : : : LDIA #00H ; set program ROM to bank1 OUTA P3 B XA1 : XA : : : LDIA #01H ; set program ROM to bank2 OUTA P3 B XB1 : XB : : : LDIA #02H ; set program ROM to bank3 OUTA P3 B XC1 : XC : : : B XD XD : : : : ;-------------------------------------------------------------------------------------BANK 1 XA1 : : : B XA : XA2 : : START:
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B XA2 : ;--------------- -------------------- -------------------- -------------------- -BANK 2 XB1 : : : B XB : XB2 : : B XB2 : ;--------------- -------------------- -------------------- -------------------- -BANK 3 XC1 : : : B XC : XC2 : : B XC2
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Fixed data can be read out by table-look-up instruction. Table-look-up instruction is requires the Data point (DP) to indicate the ROM address in obtaining the ROM code data (Except bank 0) : LDAX LDAXI Acc ROM[DP]L Acc ROM[DP]H,DP+1
DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data. User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH", then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI". PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA STADPL STADPM STADPH : LDL LDH LDAX STAMI LDAXI STAM ; ORG DATA #07h; ; [DP]L 07h ; [DP]M 07h ; [DP]H 07h, Load DP=777h
#00h; #03h;
; ACC 6h ; RAM[30] 6h ; ACC 5h ; RAM[31] 5h
1777h 56h;
DATA RAM ( 2548-nibble ) A total 2548 - nibble data RAM is available from address 000 to 9FFh Data RAM includes the zero page region, stacks and data areas. * This specification are subject to be changed without notice. 8.14.2001
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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Bank 0
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
P9=0000B 000-00Fh 010-01Fh 020-02Fh 030-03Fh 040-04Fh 050-05Fh 060-06Fh 070-07Fh 080-08Fh 090-09Fh 0A0-0AFh 0B0-0BFh 0C0-0CFh 0D0-0DFh 0E0-0EFh 0F0-0FFh Bank 1 P9=0001B 100-10Fh : : 1F0-1FFh Bank 2 P9=0010B 200-20Fh : : 2F0-2FFh Bank 3 P9=0011B 300-30Fh : : 3F0-3FFh
ZERO PAGE COM0 COM1 COM2 COM3 COM4
Level 0 Level 4 Level 8 Level 12
Level 1 Level 5 Level 8 TCA
Level 2 Level 6 Level 10 TCB
Level 3 Level 7 Level 11 DP
SPW
: : : : : : : Bank 9 P9=1001B 900-90Fh : : 9F0-9FFh
* This specification are subject to be changed without notice.
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ZERO- PAGE:
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for the instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y". PROGRAM EXAMPLE: To write immediate data "07h" to RAM [03] and to clear bit 2 of RAM [0Eh].
STD #07h, 03h ; RAM[03] 07h CLR 0Eh,2 ; RAM[0Eh]2 0
STACK: There are 13 - level (maximum) stack levels that user can use for subroutine (including interrupt and CALL). User can assign any level be the starting stack by providing the level number to stack pointer (SP). When an instruction (CALL or interrupt) is invoked, before enter the subroutine, the previous PC address is saved into the stack until returned from those subroutines, the PC value is restored by the data saved in stack. DATA AREA: Except the area used by user's application, the whole RAM can be used as data area for storing and loading general data. ADDRESSING MODE The 2548 nibble data memory consists of ten banks (bank 0 ~ bank 9). There are 244x4 bits (address 000h~0F3h) in bank 0 and 2304x4 bits (address 100h ~ 9FF) in bank 1 ~ bank 9. The bank is selected by P9. P9(3..0) Initial value : 0 0 0 0 RBK Bank RAM address(hex) 0000 0 000~0FF 0001 1 100~1FF 0010 2 200~2FF 0011 3 300~3FF 0100 4 400~4FF 0101 5 500~5FF 0110 6 600~6FF 0111 7 700~7FF 1000 8 800~8FF 1001 9 900~9FF 1 0 1 0~ 0 000~0FF 1111 The Data Memory consists of three Address mode, namely (1) Indirect addressing mode: The address in the bank is specified by the HL registers.
P9(3,2,1,0)
HR
LR
RAM address
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "032h".
OUT LDL LDH LDAM OUT LDL LDH STAM #0001B,P9 #3h #4h ; RAM bank1 ; LR 3 ; HR 4 ; Acc RAM[134h] ; RAM bank0 ; LR 2 ; HR 3 ; RAM[023h] Acc
#0000B,P9 #2h #3h
(2) Direct addressing mode: The address in the bank is directly specified by 8 bits code of the second byte in the instruction field.
instruction field xxxxxxxx P9(3..0)
RAM address
OUT LDA OUT STA #0001B,P9 43h #0001B,P9 23h
xxxxxxxx
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".
; Acc RAM[143h] ; RAM[023h] Acc
(3) Zero-page addressing mode: The zero-page is in the bank 0 (address 000h~00Fh). The address is the lower 4 bits code of the second byte in the instruction field.
instruction field yyyy
RAM address 00 00 0000 yyyy
PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".
STD #0Fh, 05h ; RAM[05h] 0Fh
* This specification are subject to be changed without notice.
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inary Prelim PROGRAM COUNTER (16K ROM)
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the instruction of program ROM instruction. For BRANCH and CALL instructions, PC is changed by instruction indicating. PC only can indicate the address from 0000h-1FFFh. The bank number is decided by P3. (1) Branch instruction: SBR a Object code: 00aa aaaa Condition: SF=1; PC PC 12-6.a ( branch condition satisified ) PC Hold original PC value+1 a a a a a a
SF=0; PC PC +1( branch condition not satisified ) PC Original PC value + 1
LBR a Object code: 1100 aaaa aaaa aaaa Condition: SF=1; PC PC 12.a ( branch condition satisified ) PC
Hold
+2
a
a
a
a
a
aa
a
a
a
a
a
SF=0; PC PC +2( branch condition not satisified ) PC Original PC value + 2
SLBR a Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh) 0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh) Condition: SF=1; PC a ( branch condition satisified ) PC a a a a a a a a a a a a a
SF=0 ; PC PC + 3 ( branch condition not satisified ) PC Original PC value + 3
(2) Subroutine instruction: SCALL a Object code: 1110 nnnn Condition : PC a ; a=8n+6 ; n=1..Fh ; a=86h, n=0 PC 0 0 0 0 0 a a a a a a a a
LCALL a Object code: 0100 0aaa aaaa aaaa Condition: PC a * This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PC 0
0
a
a
a
a
ary elimin Pr
a a a a a
a
a
RET Object code: 0100 1111 Condition: PC STACK[SP]; SP + 1 PC The return address stored in stack
RT I Object code: 0100 1101 Condition : FLAG. PC STACK[SP]; EI 1; SP + 1 PC The return address stored in stack
(3) Interrupt acceptance operation: When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into PC. The interrupt vectors are as follows : INT0 (External interrupt from P8.2) PC 0 0 0 0 0 0 0 0 0 0 0 1 0
TRGH (High speed counter interrupt) PC 0 0 0 0 0 0 0 0 0 0 1 0 0
TRGA (Timer A overflow interrupt) PC 0 0 0 0 0 0 0 0 0 0 1 1 0
TRGB (Time B overflow interrupt) PC 0 0 0 0 0 0 0 0 01 0 00
TBI (Time base interrupt) PC 0 0 0 0 0 0 0 0 01 0 10
INT1 (External interrupt from P8.0) PC 0 (4) Reset operation: PC 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 01 1 00
* This specification are subject to be changed without notice.
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(5) Other operations:
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
For 1-byte instruction execution: PC + 1 For 2-byte instruction execution: PC + 2 For 3-byte instruction execution: PC + 3 ACCUMULATOR Accumulator(ACC) is a 4-bit data register for temporary data storage. For the arithematic, logic and comparative opertion.., ACC plays a role which holds the source data and result. FLAGS There are three kinds of flag, CF (Carry flag), ZF (Zero flag) and SF (Status flag), these three 1-bit flags are included by the arithematic, logic and comparative .... operation. All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after RTI instruction is executed. (1) Carry Flag ( CF ) The carry flag is affected by the following operations: a. Addition : CF as a carry out indicator, under addition operation, when a carry-out occures, the CF is "1", likewise, if the operation has no carry-out, CF is "0". b. Subtraction : CF as a borrow-in indicator, under subtraction operation, when a borrow occures, the CF is "0", likewise, if there is no borrow-in, the CF is "1". c. Comparision : CF as a borrow-in indicator for Comparision operation as in the subtraction operation. d. Rotation : CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. CF test instruction : Under TFCFC instruction, the CF content is sent into SF then clear itself as "0". Under TTSFC instruction, the CF content is sent into SF then set itself as "1". (2) Zero Flag ( ZF ) ZF is affected by the result of ALU, if the ALU operation generates a "0" result, the ZF is "1", likewise, the ZF is "0". (3) Status Flag ( SF ) The SF is affected by instruction operation and system status. a. SF is initiated to "1" for reset condition. b. Branch instruction is decided by SF, when SF=1, branch condition is satisified, likewise, when SF = 0, branch condition is unsatisified.
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE: Check following arithematic operation for CF, ZF, SF
LDIA #00h; LDIA #03h; ADDA #05h; ADDA #0Dh; ADDA #0Eh; CF ZF 1 0 0 0 0
ary elimin Pr
SF 1 1 1 0 0
ALU The arithematic operation of 4-bit data is performed in ALU unit. There are 2 flags that can be affected by the result of ALU operation, ZF and SF. The operation of ALU is affected by CF only. ALU STRUCTURE ALU supported user arithematic operation functions, including Addition, Subtraction and Rotaion.
DATA BUS
ALU
ZF CF SF
ALU FUNCTION (1) Addition: ALU supports addition function with instructions ADDAM, ADCAM, ADDM #k, ADD #k,y .... . The addition operation affects CF and ZF. Under addition operation, if the result is "0", ZF will be "1", otherwise, ZF will be "0". When the addition operation has a carry-out, CF will be "1", otherwise, CF will be "0". EXAMPLE:
Operation 3+4=7 7+F=6 0+0=0 8+8=0 Carry 0 1 0 1 Zero 0 0 1 1
(2) Subtraction: ALU supports subtraction function with instructions SUBM #k, SUBA #k, SBCAM, DECM... . The subtraction operation affects CF and ZF. Under subtraction operation, if the result is negative, CF will be "0", and a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction operation is "0", the ZF is "1", likewise, ZF is "1".
* This specification are subject to be changed without notice.
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EXAMPLE:
Operation 8-4=4 7-F= -8(1000) 9-9=0
inary Prelim
Carry 1 0 1 Zero 0 0 1
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
(3) Rotation: Two types of rotation operation are available, one is rotation left, the other is rotation right. RLCA instruction rotates Acc value counter-clockwise, shift the CF value into the LSB bit of Acc and hold the shift out data in CF.
MSB LSB ACC CF
RRCA instruction operation rotates Acc value clockwise, shift the CF value into the MSB bit of Acc and hold the shift out data in CF.
MSB LSB ACC CF
TTCFS; CF 1 RRCA; rotate Acc right and shift CF=1 into MSB.
PROGRAM EXAMPLE: To rotate Acc clockwise (right) and shift a "1" into the MSB bit of Acc.
HL REGISTER HL register are two 4-bit registers, they are used as a pair of pointer for the RAM memoryaddress. They are used as also 2 independent temporary 4-bit data registers. For certain instructions, L register can be a pointer to indicate the pin number (Port4 only). HL REGISTER STRUCTURE
3210 3210
H REGISTER L REGISTER
HL REGISTER FUNCTION (1) HL register is used as a temporary register for instructions : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH. PROGRAM EXAMPLE: Load immediate data "5h" into L register, "0Dh" into H register.
LDL #05h; LDH #0Dh;
(2) HL register is used as a pointer for the address of RAM memory for instructions : LDAM, STAM, STAMI .. PROGRAM EXAMPLE: Store immediate data "#0Ah" into RAM of address 35h. * This specification are subject to be changed without notice. 8.14.2001
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
LDL #5h; LDH #3h; STDMI #0Ah; RAM[35] Ah
ary elimin Pr
(3) L register is used as a pointer to indicate the bit of I/O port for instructions : SELP, CLPL, TFPL, (When LR = 0 indicate P4.0)
LDL #00h; SEPL ; P4.0 1
PROGRAM EXAMPLE: To set bit 0 of Port4 to "1"
STACK POINTER (SP) Stack pointer is a 4-bit register that stores the present stack level number. Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition. When a new subroutine is received, the SP is decreased by one automatically, likewise, if returning from a subroutine, the SP is increased by one. The data transfer between ACC and SP is done with instructions "LDASP" and "STASP". DATA POINTER (DP) Data pointer is a 12-bit register that stores the ROM address can indicating the ROM code data specified by user (refer to data ROM). CLOCK AND TIMING GENERATOR The clock generator is supported by a dual clock system. The high-frequency oscillator is internal oscillator. The low-frequency oscillator may be sourced from crystal, the working frequency is 32 KHz. CLOCK GENERATOR STRUCTURE There are two clock generator for system clock control unit, P14 is the status register that hold the CPU status. P16, P19 and P22 are the command register for system clock mode control.
Mask option for choose Crystal or RC oscillator
XIN XOUT LXIN
High-frequency generator Low-frequency generator
fc
P14
fs
System clock mode control
P16 P19 P22
LXOUT
Mask option for choose Crystal or RC oscillator
System control
Res
LXIN/XIN
LXIN/XIN
LXOUT/XOUT
LXOUT/XOUT
Crystal connection
or
RC connection
( Res=100K for high frequency osc / Res=1M for slow frequency osc)
* This specification are subject to be changed without notice.
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SYSTEM CLOCK MODE CONTROL
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator and switch between the basic clocks. EM73P968 has four operation modes (NORMAL, SLOW, IDLE and STOP operation modes).
STOP operation mode High osc : stopped Low osc : stopped
I/O wakeup Reset
Command (P16)
Reset
NORMAL operation mode
High osc : oscillating Low osc : oscillating Command (P22) Command (P22)
Command (P16)
Reset release
RESET operation
Reset
SLOW operation mode
High osc : stopped Low osc : oscillating
Reset
Command (P19)
I/O or internal timer wakeup
IDLE (CPU stops)
High osc : stopped Low osc : oscillating
Operation Mode NORMAL SLOW IDLE STOP
Oscillator System Clock High, Low frequency High frequency clock Low frequency Low frequency clock Low frequency CPU stops None CPU stops
Available function LCD, SPI, A/D, HTC. LCD LCD All disable
One instruction cycle 8 / fc 4 / fs -
NORMAL OPERATION MODE The 4-bit c is in the NORMAL operation mode when the CPU is reseted. This mode is dual clock system (high-frequency and low-frequency clocks oscillating). It can be changed to SLOW or STOP operation mode with the command register (P22 or P16). LCD display and high speed timer/counter are available for the NORMAL operation mode. SLOW OPERATION MODE The SLOW operation mode is single clock system (low-frequency clock oscillating). It can be changed to the NORMAL operation mode with the command register (P22), STOP operation mode with P16 and IDEL operation mode with P19. LCD display is available for the SLOW operation mode.
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
P22
3 *
2
1 SOM
0
Initial value : 0000
ary elimin Pr
SOM 000 001 010 011 1** P14
Low-frequency 2^3/LXIN RC solw to normal 2^4/LXIN RC solw to normal 2^11/LXIN X'tal slow to normal 2^12/LXIN X'tal slow to normal normal to slow Initial value : *000 CPUS 0 1 CPU status NORMAL operation mode SLOW operation
3 2 1 0 INT2_S WKS SPI_F CPUS
SPI_F 0 1 WKS 0 1
SPI_Flag SPI register is empty SPI register is full Wakeup status Wakeup not by internal timer Wakeup by internal timer
Port14 is the status register for CPU. P14.0 (CPU status) and. P14.2 (wakeup status) will be set to "1" when CPU is wake-up by internal timer. P14.2 will be cleared to "0" when user out data to P14. INT2_S is low, the program address "0004H" is the interrupt entry address of HTCI. INT2_S is high, the program address "0004H" is the interrupt entry address of ADI. IDLE OPERATION MODE The IDLE operation mode suspends all CPU functions except the low-frequency clock oscillation and the LCD driver. It keeps the internal status with low power consumption without stopping the slow clock oscillator and LCD display. LCD display is available for the IDLE operation mode. The IDLE operation mode will be wakeup and return to the SLOW operation mode by the internal timing generator or I/O pins (P0(0..3)/WAKEUP 0..3, P1(0..3)/ WAKEUP 4..7, P2(0..3)/WAKEUP 8..11, P4(0..3)/WAKEUP 12..15, P5(0..3)/WAKEUP 16..19, P6(0.. 3)/WAKEUP 20..23, P7(0..3)/WAKEUP 24..27, P8(0..3)/WAKEUPA..D, P11(0..3)/WAKEUP 28..31, and P15(0..3)/WAKEUP 32..35). P19
3 2 IDME 1 0 SIDR
Initial value : 0000 SIDR 00 01 10 11 Select IDLE releasing condition P0,P1,P2,P4,P5,P6,P7,P8,P11,P15 pin input P0,P1,P2,P4,P5,P6,P7,P8,P11,P15 pin input and 1 sec signal P0,P1,P2,P4,P5,P6,P7,P8,P11,P15 pin input and 0.5 sec signal P0,P1,P2,P4,P5,P6,P7,P8,P11,P15 pin input and 15.625 ms signal 8.14.2001
19
IDME 01 **
Enable IDLE mode Enable IDLE mode no function
* This specification are subject to be changed without notice.
STOP OPERATION MODE
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
The STOP operation mode suspends system operation and holds the internal status immediately before the suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/ WAKEUP 0..3, P1(0..3)/WAKEUP 4..7, P2(0..3)/WAKEUP 8..11, P4(0..3)/WAKEUP 12..15, P5(0..3)/ WAKEUP 16..19, P6(0..3)/WAKEUP 20..23, P7(0..3)/WAKEUP 24..27, P8(0..3)/WAKEUPA..D, P11 (0..3)/WAKEUP 28..31, and P15(0..3)/WAKEUP 32..35). LCD display and high speed timer/counter with melody output are disabled in STOP mode. Initial value : 0000 P16 3
* *
210 SWWT 100 01 110 111
* 1 * *
Set wake up Stop wake up time (go to NORMAL) 2^9/XIN for RC osc. 2^10/XIN for RC osc. 2^18/XIN for Crystal osc. 2^19/XIN for Crystal osc.
GENERAL PURPOSE REGISTER (P10) P10 is a 4-bit general purpose register which can be read, written and rested by all I/O instructions. (including : INA, INM, OUT, OUTA, OUTM, SEP, CLP, TTP, TFP) PROGRAM EXAMPLE: CHIP ROM16K ;--------RAM define area-----------------
DSEG ORG 10H HLBUF: RES 2 ; HL buffer for interrupt P9BUF: RES 1 ; P9 (RAM bank) buffer for interrupt : ;----------Interrupt subroutine-------------------CSEG ORG 004H LBR HTCI : HTCI: OUTA P10 ; save Acc to general purpose register P10 INA P9 OUT #0000B,P9 STA P9BUF ; save RAM bank to P9BUF EXHL HLBUF ; save HL to HLBUF : : EXHL HLBUF ; restore HLBUF to HL LDA P9BUF ; resotre P9BUF to RAM bank OUTA P9 INA P10 ; restore register P10 to Acc RTI
10 instruction bytes
10 instruction bytes
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TIME BASE INTERRUPT (TBI)
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The time base can be used to generate a single fixed frequency interrupt. Eight types of frequencies can be selected with the "P25" setting.
P25 3 2 1 0 initial value : 0000
0 0 0 0 0 1 1 1 1 1
P25 0x 10 10 11 11 10 10 11 11 0x
x 0 1 0 1 0 1 0 1 x
NORMAL operation mode Interrupt disable Interrupt frequency LXIN / 23 Hz Interrupt frequency LXIN / 215 Hz Interrupt frequency LXIN / 25 Hz Interrupt frequency LXIN / 214 Hz Interrupt frequency LXIN / 21 Hz Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved
SLOW operation mode Interrupt disable Reserved Interrupt frequency LXIN / 215 Hz Reserved Interrupt frequency LXIN / 214 Hz Reserved Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 210 Hz Reserved
TIMER / COUNTER (TIMERA, TIMERB) Timer/counters support three special functions: 1. Even counter 2. Timer. 3. Pulse-width measurement. These three functions can be executed by 2 timer/counter independently. With timerA, the counter data is saved in timer register TAH, TAM, TAL. User can set counter initial value and read the counter value by instruction "LDATAH(M,L)" and "STATAH(M,L)". With timer B register is TBH, TBM, TBL and the W/R instruction are "LDATBH (M,L)" and "STATBH (M,L)". The basic structure of timer/counter is composed by two identical counter module, these two modules can be set initial timer or counter value to the timer registers, P28 and P29 are the command registers for timerA and timer B, user can choose different operation modes and internal clock rates by setting these two registers. When timer/counter overflows, it will generate a TRGA(B) interrupt request to interrupt control unit. INTERRUPT CONTROL
TRGA request DATA BUS
12 BIT COUNTER
TRGB request
12 BIT COUNTER
P8.3/ TRGA internal clock
EVENT COUNTER CONTROL TIMER CONTROL PULSE-WIDTH MEASUREMENT CONTROL
EVENT COUNTER CONTROL TIMER CONTROL PULSE-WIDTH MEASUREMENT CONTROL
P8.1/ TRGB
internal clock
P28
TMSA
IPSA
P29
TMSB
IPSB
* This specification are subject to be changed without notice.
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inary Prelim
TIMER/COUNTER CONTROL
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event counter and pulse-width measurement mode. Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/ counterB. P28, P29 3 2 1 0 Initial value : 0000
TMSA(B) IPSA(B)
TMSA(B) 00 01 10 11 IPSA 00 01 10 11
Mode selection Stop Event counter mode Timer mode Pulse width measurement mode Clock rate selection NORMAL mode SLOW mode Reserved LXIN/23 HZ LXIN/27 HZ LXIN/27 HZ LXIN/211 HZ LXIN/211 HZ 15 LXIN/2 HZ LXIN/215 HZ IPSB 00 01 10 11 Clock rate selection NORMAL mode SLOW mode Depend on high speed timer/counter LXIN/25 HZ LXIN/25 HZ LXIN/29 HZ LXIN/29 HZ 13 LXIN/2 HZ LXIN/213 HZ
TIMER/COUNTER FUNCTION Timer/counterA,B are programmable for timer, event counter and pulse width measurement mode. Each timer/counter can execute any of these functions independently. EVENT COUNTER MODE Under event counter mode, the timer/counter is increased by one at any rising edge of P8.1/TRGB for timerB (P8.3/TRGA for timer A). When timerB (timerA) counts overflow, it will provide an interrupt request TRGB (TRGA) to interrupt control unit.
P8.1/TRGB (P8.3/TRGA)
TimerB (TimerA) value n
n+1
n+2
n+3
n+4
n+5
n+6
PROGRAM EXAMPLE: Enable timerA with P28
LDIA OUTA #0100b; P28 ; Enable timerA with event counter mode
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TIMER MODE
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Under timer mode, the timer/counter is increased by one at any rising edge of internal pulse. User can choose up to 4 types of internal pulse rate by setting IPSB for timerB (IPSA for timerA). When timer/counter counts overflow, an interrupt request will be sent to interrupt control unit.
Internal pulse
TimerB (TimerA )value
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock LXlN=32KHz
LDIA #0100B EXAE EICIL 110111b LDIA #0Ah; STATAL; LDIA #00h; STATAM; LDIA #0Fh; STATAH; LDIA #1000B; OUTA P28 ; ; enable mask 2 ; interrupt latch 0, enable EI
; enable timerA with internal pulse rate: LXIN/23 Hz
NOTE:
The preset value of timer/counter register is calculated as following procedure. Internal pulse rate: LXIN/23 ; LXIN = 32KHz The time of timer counter count one = 23 /LXIN = 8/32768=0.244ms The number of internal pulse to get timer overflow = 60 ms/0.244ms = 245.901= 0F6h The preset value of timer/counter register = 1000h - 0F6h = F0Ah
PULSE WIDTH MEASUREMENT MODE Under the pulse width measurement mode, the counter is incresed at the rising edge of internal pulse during external timer/counter input (P8.1/TRGB, P8.3/TRGA) in high level, interrupt request is generated as soon as timer/counter count overflow.
P8.1/TRGB(P8.3/TRGA)
Internal pulse
TimerB(TimerA) value
n
n+1
n+2
n+3
n+4
n+5
PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode.
LDIA OUTA #1100b ; P28 ; Enable timerA with pulse width measurement mode.
* This specification are subject to be changed without notice.
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HIGH SPEED TIMER/COUNTER
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
EM73P968 has one 8-bit high speed timer/counter (HTC). It supports two special functions : auto load timer and melody output. The HTC is available for the NORMAL and SLOW operation mode. The HTC can be set initial value and send counter value to counter registers (P12 and P13), P20 is the command port for HTC, user can choose different operation mode and different internal clockrate by setting the port. The timer/counter increase one at the rising edge of internal pulse. The HTC can generate an overflow interrupt (HTCI) when it overflows. The HTCI cannot be generated when the HTC is in the melody mode or disabled.
INTERRUPT FUNCTION Six interrupt sources are available, 2 from external interrupt sources and 4 from internal interrupt sources. Multiple interrupts are admitted according to their priority.
Interrupt source Priority Interrupt Interrupt Latch Enablecondition IL5 IL4 IL3 IL2 IL1 IL0 EI=1 EI=1,MASK3=1 EI=1,MASK2=1 EI=1,MASK1=1 EI=1, MASK0=1 ProgramROM entry address
Type
External Internal Internal Internal Internal External
External interrupt (INT0) HTC interrupt (HTCI) TimerA overflow interrupt (TRGA) TimerB overflow interrupt (TRGB) Time base interrupt(TBI) Externalinterrupt(INT1)
1 2 3 4 5 6
002h 004h 006h 008h 00Ah 00Ch
INTERRUPT STRUCTURE
MASK0 MASK1 MASK1 MASK2 MASK3 INT1 r0 Reset by system reset and program instruction IL0 TBI r1 IL1 TRGB TRGA r2 r3 IL2 IL3
HTCI/ADI
r4 IL4
INT0 r5 IL5
Priority checker Reset by system reset and program instruction Set by program instruction EI
Entry address generator
Interrupt request
Interrupt entry address
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Interrupt controller: IL0-IL5
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: Interrupt latch. Hold all interrupt requests from all interrupt sources. IL's can not be set by program, but can be reset by program or system reset, so IL can only decide which interrupt source can be accepted. : Except INT0, MASK register may permit or inhibit all interrupt sources. : Enable interrupt Flip-Flop may promit or inhibit all interrupt sources, when interrupt occurs, EI is auto cleared to "0", after RTI instruction is executed, EI is auto set to "1" again. : Check interrupt priority when multiple interrupts occur.
MASK0-MASK3 EI
Priority checker
INTERRUPT OPERATION The procedure of interrupt operation: 1. Push PC and all flags to stack. 2. Set interrupt entry address into PC. 3. Set SF = 1. 4. Clear EI to inhibit other interrupts occur. 5. Clear the IL with which interrupt source has already been accepted. 6. Excute interrupt subroutine from the interrupt entry address. 7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests. PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA"
LDIA EXAE EICIL #0100B ; ; set mask register "1100b" 010111B ; enable interrupt F.F. and clear IL3 and IL5
HIGH SPEED COUNTER EM73P968 has one high speed counter for auto load timer mode. This function is available for the NORMAL operation mode.
P20(3,2)
8-bit binary counter P20(1,0)
Overflow
HTCI interrupt Timer/counter B
Reload P12 P13 Data bus
XIN
* This specification are subject to be changed without notice.
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inary Prelim
CONTROL OF HIGH SPEED COUNTER
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
The high speed counter is controlled by the command registers (P20) : P20 3 2 1 0 RATE Selection of HTC mode Disable HTC Auto load timer mode Reserved Reserved Initial value : 0000
MODE MODE 00 01 10 11 RATE ( Hz )
Internal pulse rate / Counter start request frequency Auto load timer mode / Melody mode internal pulse rate 00 CLK / 2" 01 CLK / 2# 10 CLK / 2$ 11 CLK / 2% Note : CLK is high frequency. P12 and P13 are the 8-bit binary counter registers of the HTC. P12 is lower nibble register and P13 is higher nibble register. P13 3 2 1 0 Higher nibble register P12 3 2 1 0 Lower nibble register Initial value : 0000 0000
The HTC can be set initial value and send counter value to counter registers (P13 and P12), and P20 are the command ports for HTC, user can choose different operation mode and different internal clockrate. The timer/counter increase one at the rising edge of internal pulse. The HTC can generate an overflow interrupt (HTCI) when it overflows. The HTCI can not be generated when the HTC is disabled. The value of 8-bit binary up counter can be presetted by P12 and P13. The value of registers can loaded into the HTC when the counter starts counting or occurs overflow. If user write value to the registers before the next overflow occurs, the preset value can be changed. The preset value will be changed when users output the different data to P12 and P13. The count value of HTC can be read from P12 and P13. The value is unstable when user read the value during counting. Thus, user must disable the counter before reading the value.
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
FUNCTION OF HIGH SPEED COUNTER The HTC has auto load timer mode.
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The HTC is disabled when the CPU is reseted or in the SLOW/STOP/IDLE operation mode. Users must enable it by self when the CPU is waked up. Auto load timer mode In this mode, there are four different internal pulse rates can be selected by P20. The HTC loads the initial values by the counter registers (P12, P13) and increases at the rising edges of internal pulse generated by the time base. The value of TCB increases one when the high speed counter overflows and generates an overflow interrupt (TRGB) when the TCB overflows. This mode is only available for NORMAL operation mode. PROGRAM EXAMPLE : LDIA #00H STATBL STATBM STATBH OUTA P13 OUTA P12 LDIA #1011B OUTA P20 : LDIA #00H OUTA P20 INA P12 STA 00H INA P13 STA 01H LDATBL STA 02H LDATBM STA 03H LDATBH STA 04H ; initial TCB & HTC register
; enable timer mode, internal pulse rate : CLK/27 ; disable timer mode ; store the counter value to RAM[00] - RAM[04]
* This specification are subject to be changed without notice.
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ANALOG TO-DIGITAL CONVERTER (ADC)
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
The analog to - digital consists of an 8-bit analog multiplexer (P6, P7), one control register (P26), two data register (P12,P13), and ADC with 8-bit resolution. The ADC module utilizes successive approximation to convert the unknown analog signal to a digital value. The result is fed to the P12,P13, Input channel are select by the analog input multiplexer the P17 register bits SEL0, SEL1 and SEL2. The A/D converter is disable when the CPU is reset or in the STOP/IDLE/SLOW operation mode. User must enable it by self when the CPU is NORMAL operation mode.
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VAD
8-1 bit analog Switch
Vref
ADC
VADSS (GND) 01234567 P12, P13 P26
3 123
013
MUX 01 CTR
INT2_S
SEL
DATA
A/D channel control register P17(BIT) SYMBOL 3 SEL2 2 SEL1 1 SEL0
BUS
0 COM4
Initial value :0000
SEL0~ SEL2: Analog Input select A/D input share with P6 & P7. Analog Input Select Input channel Share with pin SEL2 SEL1 SEL0 0 0 0 AIN0 P6.0 0 0 1 AIN1 P6.1 0 1 0 AIN2 P6.2 0 1 1 AIN3 P6.3 1 0 0 AIN4 P7.0 1 0 1 AIN5 P7.1 1 1 0 AIN6 P7.2 1 1 1 AIN7 P7.3
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ADC control register P26(BIT) SYMBOL 3 ADEN 2 *
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1 F_RUN 0 START Initial value : 0000
Port 26 is A/D control register , when P26.3 (ADEN) is high A/D converter enable , P26.3 is low A/D converter disable , P26.1(F_RUN) is high, select A/D conversion is free run , P26.1(F_RUN) is slow , A/D could not convert P26.0(START) is high , A/D converter is only one time. A/D clock rate control register P23(BIT) SYMBOL A/D 0 0 1 1 rate 0 1 0 1 3 * 2 * 1 0 Initial value : 0000 A/D rate select
A/D clock rate CLK / 25 CLK / 26 CLK / 27 CLK / 27
CLK=system clock (4M) ADC Data Register (P12,P13) When we use ADC , first ADC must get P12,P13 ,because P12,P13 share with SPI , ADC and HTC when the A/D conversion is complete ,the result is load to the P12,P13, and the ADC can generate an interrupt (ADI), the INT2_S ( P14.3) is set high.
* This specification are subject to be changed without notice.
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inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE : input P6.0 an analog message to coverter CHIP 16K ;---------------------- RAM define area ---------------------DSEG 10H ADCBUF: RES 2 ;---------------------- interrupt subroutine ---------------------CSEG LBR START ORG 004H LBR ADI ;----------------------------------------------------------------------START: LDIA #0001B ; A/D clock rate=60K OUTA P23 LDIA #0001B OUTA P18 ; P12,P13 ADC LDIA #1001B OUTA P26 ; ADC enable & ADC run one time LDIA #0000B OUTA P17 ; P6.0 input an analog LOOP: B LOOP ; wait the ADC interrupt to occur & interrupt Flag to be Set (INT2 _S) B LOOP : : ADI: INA P12 STA ADBUF INA P13 STA ADBUF RET
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
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SERIAL PERIPHERAL INTERFACE (SPI) The Serial Peripheral Interface (SPI) circuitry consists of two control register P18, P24 , one data register (P12, P13) ,one shift register. The MSTR select the source of the serial clock from the internal or the external clock. at the same time, only transfer can occur or receive can occur. The SPI is available for the NORMAL operation mode.
Internal SPI_F MSTR CTR0~1 2 DCOL
bus SPIE 8
DORD
SPI reg
P12, P13
CLK0~1 2
8
CLOCK GENERATOR
8-BIT Shift register
Output latch
SDO SDI SCK
P15
SPI Control Register : P24(Bit) SYMBOL 3 2 MSTR DORO 1 CLKS1 0 CLKS0
CLKS0~CLKS1: SPI transmission clock rate select This is the clock rate selection bits, on master mode, we have four Kinds of rate can select. P24(1,0 BIT) CLKS1 CLKS0 Fc/2^5 0 0 Fc/2^6 0 1 Fc/2^7 1 0 Fc/2^8 1 1 DORD: Data transmission order 0: LSB first the data in the 8-bit shift register is shifted in/out LSB first 1: MSB first the data in the 8-bit shift register is shifted in/out LSB first Clock Rate
* This specification are subject to be changed without notice.
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inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
MSTR: master or slave mode select 0: Master mode SPI is in master mode and SCK is configured as an output pin. SPI clock source is internal clock. 1: slave mode SPI is in slave mode and SCK is configured as an input pin. SCK receives the serial clock externally. P18(Bit) SYMBOL 3 SPIE 2 * 1 CTR1 0 CTR0
SPIE: Serial Peripheral Interface Enable 1: Serial Peripheral Interface Enable 0: Serial Peripheral Interface disable P12, P13 control table CTR1 CTR0 0 0 0 1 1 0 1 1 Select resume HTC counter A/D converter SPI shift data Unused
SPI control bit: SPI_F( P14.1): SPI control flag when SPI register (P12, P13) is empty SPI_F clear 0 when SPI register (P12, P13) is full, SPI_F set 1 P3(Bit) 3 SYMBOL DCOL 2 * 1 0 ROM bank select
DCOL (P3.3): SPI control flag When SPI shift register is empty DCOL clear 0. When SPI shift register is full DCOL set 1. SDO: Serial data out ( share with P15.0) When MSTR set to 0 , SDO is an output pin, share with P15.0, When the SPI is enable , data are shift out form SDO (P15.0) SDI: Serial data out (share with P15.0) When MSTR set to 1 , SDI is an input pin, share with P15.0, When the SPI is enable , data are shift in form SDI (P15.0) SCK: Serial Clock (share with P15.1) The SCK pin for synchronization of both input and output data stream through SDI and SDO pins. When the MSTR is set, SCK become an output and the Serial clock is supplied to the internal system. When the MSTR is clear, SCK become an intput and the Serial clock is supplied to the external system. The clock speed in slave mode is dependent upon the speed of the external system and has a maximum speed up till the internal system clock. * This specification are subject to be changed without notice. 8.14.2001
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SCK: Serial Clock (share with P15.1) The SCK pin for synchronization of both input and output data stream through SDI and SDO pins. When the MSTR is set, SCK become an output and the Serial clock is supplied to the internal system. When the MSTR is clear, SCK become an intput and the Serial clock is supplied to the external system. The clock speed in slave mode is dependent upon the speed of the external system and has a maximum speed up till the internal system clock. PROGRAM EXAMPLE : transmission 16 bit (ABAB H) serial data LBS first, clock rate Fc/2^8 (Fc=4MHz) LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA SEP TTP B LDIA OUTA LDIA OUTA SEP TTP B TTP B LDIA OUTA #1010B P18 #0011B P24 #0AH P13 #0BH P12 P14,1 P14,1 NEXT #0AH P13 #0BH P12 P14,1 P14,1 NEXT1 P3.3 NEXT2 #0 P18 ; enable SPI & P12,P13a SPI ; transmission LBS first & Fc/2^8 clock rate ; 0AH P13, ; 0BH P12 ; SPI register (P12, P13) is full ; wait SPI register is empty and input next data (8 bits) ; 0AH P13 ; 0BH P12 ; wait SPI register is empty and input next data (8 bits)
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NEXT:
NEXT1: NEXT2:
; wait all data transfer over ; SPI disable
* This specification are subject to be changed without notice.
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SPI TIMING DIAGRAM DATA OUTPUT TIMING
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SCK SDO MSTR=0 DORD=0 SDO MSTR=0 DORD=1 DATA SAMPLE SPI_F
MSB BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 LSB
LSB BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 MSB
DATA INPUT TIMING
SCK SDO MSTR=0 DORD=0 SDO MSTR=0 DORD=1 DATA SAMPLE SPI_F
MSB BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 LSB
LSB BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 MSB
* This specification are subject to be changed without notice.
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EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
LCD DRIVER
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EM73P968 can directly drive the liquid crystal display (LCD) and has 52 segment and 4 or 5 common output pins by mask option. There are total 52x4 or 52x5 dots can be display. The VRLC pin is the LCD driver power input, there is the voltage of (VCC-VRLC) to LCD. P17.0 share with com 4. When the mask option select 1/4 duty, the P17.0 is an output pin and LCD have 4 common. When the mask option select 1/5 duty, the P17.0 is a LCD pin and LCD have 5 common. LCD driver control command register (P27) : Port27 3210 Initial value : 0000 LDC * * * LDC LCD display control 0 LCD display disable 1 LCD display enable * : Don't care. Example :
LDIA OUTA : LDIA OUTA #1000B P27 #0000B P27 ; enable LCD, reference voltage of LCD is 1.5V.
; disable LCD
LCD RAM
0 20H-2CH 30H-3CH 40H-4CH 50H-5CH 60H-6CH 1 2 3 4 COM0 COM1 COM2 COM3 COM4
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51
5
6
7
8
9
A
B
C
D
E
F
* This specification are subject to be changed without notice.
8.14.2001
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Driving Method 1/5 duty 1/4 duty Driving Method 1/5 duty 1/4 duty -
RAM address 20H 30H 40H 50H 60H RAM address 21H 31H 41H 51H 61H
inary Prelim
SEG0 bit0
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SEG1 bit1
SEG2 bit2
SEG3 bit3
SEG4 bit0
SEG5 bit1
SEG6 bit2
SEG7 bit3
: :
Driving Method 1/5 duty 1/4 duty RAM address 2CH 3CH 4CH 5CH 6CH SEG48 bit0 SE49 bit1 SEG50 bit2 SEG51 bit3
(1) 1/5 duty (1/3 bias)
COM0
V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss -V1 -V2 -V3 V3 V2 V1 Vss -V1 -V2 -V3
(2) 1/4 duty (1/3 bias)
COM0
V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss V3 V2 V1 Vss
COM1
COM1
COM2
COM2
COM3
COM3
COM4
SEG0
SEG0
V3 V2 V1 Vss V3 V2 V1 Vss -V1 -V2 -V3 V3 V2 V1 Vss -V1 -V2 -V3
SEG0-COM0 ON
SEG0-COM0 ON
SEG0-COM1 OFF
Frame
SEG0-COM1 OFF
Frame
* This specification are subject to be changed without notice.
8.14.2001
36
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
WATCH-DOG-TIMER (WDT)
ary elimin Pr
Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a timeup signal every certain time. User can use the time up signal to give system a reset signal when system is fail. This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when CPU is reseted or in the STOP operation mode. The basic structure of Watch-Dog-Timer control is composed by a 4-stage binary counter and a control unit. The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the counter will be cleared and continue counting. Otherwise, if there is a malfunction happened, the WDT control will send a WDT signal (low active) to reset CPU. The WDT checking period is assign by P21 (WDT command port).
WDT counter 0 1 2 13 LXIN/2 3 RESET pin counter clear request mask option WDT control
P21 WDT command port
P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to RESET. Port 21 CWC 0 1 WDT 0 1
CWC
3
*
2
*
1
WDT
0
Initial value :0000
Clear watchdog timer counter Clear counter then return to 1 Nothing Set watch-dog-timer detect time 3 x 213/LXIN = 3 x 213/32K Hz = 0.75 sec 7 x 213/LXIN = 7 x 213/32K Hz = 1.75 sec
PROGRAM EXAMPLE To enable WDT with 7 x 213/LXIN detection time.
LDIA #0001B OUTA P21 ; set WDT detection time and clear WDT counter : :
* This specification are subject to be changed without notice.
8.14.2001
37
RESETTING FUNCTION
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
When CPU in normal working condition and RESET pin is held in low level for three instruction cycles at least, then CPU begins to initialize the whole internal states, when RESET pin changes to high level, CPU begins to work in normal condition. The CPU internal state during reset condition is as following table : Hardware condition in RESET state Program counter Status flag Interrupt enable flip-flop ( EI ) MASK0 ,1, 2, 3 Interrupt latch ( IL ) P3, 9, 10, 12, 13, 14, 16, 19, 20, 21, 22, 25, 27, 28, 29 P0, 1, 2, 4, 5, 6, 7, 8, 11, 15, 17, 30, 31 LXIN, XIN Initial value 0000h 01h 00h 00h 00h 00h 0Fh Start oscillation
The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option. The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
* This specification are subject to be changed without notice.
8.14.2001
38
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ary elimin Pr
EM73P968 I/O PORT DESCRIPTION :
Port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 I E E E E I E E E E E I I E Input function Input port, wakeup function Input port, wakeup function Input port, wakeup function ROM bank selection Input port, wakeup function Input port, wakeup function Input port, wakeup function share with A/D input Input port, wakeup function share with A/D input Input port, wakeup function, external interrupt input RAM bank selection General purpose register Input port, wakeup function SPI input data register SPI input data register CPU status Input port, wakeup function P15.0 input data with SPI, P15.1 input clock with SPI Output function E E I E E E E E I I E I I I E I I I I I I I I I I I I I I Output port Output port ROM bank selection, P3.3 SPI use Output port Output port Output port Output port Output port, P8.0(INT1), P8.1(TRGB), P8.2(INT0), P8.3(TRGA) RAM bank selection General purpose register Output port High speed counter register share with SPI output data, A/D resolution data High speed counter register share with SPI output data, A/D resolution data CPU status, interrupt source selector Output port, P15.0 output data with SPI, P15.1 output clock with SPI STOP mode control register Output port P17.0/COM4 P17.1-P17.3 A/D control register Interrupt status register P12, P13 control register IDLE mode control register HTC control register WDT control register NORMAL/SLOW mode control register ADC control register SPI control register Timebase control register A/D control register LCD control register Timer / counter A control register Timer / counter B control register Output port / SEG(51..48) Output port / SEG(47..44) Note
Low nibble High nibble
* This specification are subject to be changed without notice.
8.14.2001
39
RESET PIN TYPE
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TYPE RESET-A
RESET
mask option
OSCILLATION PIN TYPE
TYPE OSC-A
XIN
TYPE OSC-B
LXIN
Crystal Osc.
XOUT LXOUT
Crystal Osc.
TYPE OSC-H1 (Low frequency)
VDD 1Mohm LXIN
TYPE OSC-H2 (High frequency)
VDD
RC Osc.
10Kohm
OSC
RC Osc.
INPUT PIN TYPE
TYPE INPUT-K
input data
WAKEUP mask option negative edge detector
: mask option
I/O PIN TYPE
TYPE I/O-N
TYPE I/O-O
path B path A Input data
TYPE I/O-N
Output data latch
Output data Special function output
: mask option
: mask option
* This specification are subject to be changed without notice.
8.14.2001
40
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TYPE I/O-Q
ary elimin Pr
TYPE I/O-R1
path B path A Input data
TYPE I/O-Q
Output data latch
Output data Special function output
: mask option
WAKEUP function mask option
TYPE I/O-S
path B path A
SEL
TYPEI/O-Z
Special function control input Input data
Output data latch
TYPE I/O-Q
path B path A
Input data Power-on reset Output data Special function output
TYPE I/O-N
Output data : mask option
Output S R data latch
WAKEUP function mask option
OUTPUT-L
OUTPUT-M
TYPE I/O-Q
Output data latch
Output data Special function output
TYPE I/O
Output data latch
Output data Special function output
: mask option
: mask option
Path A : Path B :
For set and clear bit of port instructions, data goes through path A from output data latch to CPU. For input and test instructions, data from output pin go through path B to CPU and the output data latch will be set to high.
* This specification are subject to be changed without notice.
8.14.2001
41
inary Prelim ABSOLUTE MAXIMUM RATINGS
Items Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Sym. VDD V IN VO PD T OPR TSTG
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Ratings -0.5V to 6V -0.5V to VDD+0.5V -0.5V to VDD+0.5V 300mW -30oC to 70oC -55oC to 125oC
Conditions
TOPR=50 oC
RECOMMANDED OPERATING CONDITIONS
Items Supply Voltage Sym. VDD Ratings Min. Normal 2.2V Slow 2.2V Idle 2.2V Stop 2.0V 0.80xVDD to VDD 0V to 0.20 to VDD 4MHz 32KHz Max. 6.0V VDD : 2.0~5.5V Osc LXIN, LXOUT (crystal osc) Condition 4MHz by RC osc
Input Voltage schmitt circuit Operating Frequency
V IH V IL FC Fs
AD CONBERTER CHARACTERISTICS (V),=5.0V, V4-.=5.0V, V55=0V)
Characteristic Resolution Conversion range Quantization error Sampling rate A/D supply current Analog input impedance Vref current Sym. -
Min.
8 V SS
Max.
8 VAD +1 10 1.0 5 3 0.2
Unit
bit V LSB CLK mA A M mA
Condition VAD =5V VDD =5V ADEN=0 ADEN=1
AIDD1 AIDD2 RAN AIref
-
-
* This specification are subject to be changed without notice.
8.14.2001
42
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ary elimin Pr
DC ELECTRICAL CHARACTERISTICS (VDD=50.5V, VSS=0V, TOPR=25oC) Parameters
Supply current
Sym.
I DD_Xtal
Min.
-
Typ.
1.5 100 80 0.1 650 80 45 0.1 14 550 60 24 11 55 22 450 55 20 55 20 20
Max.
2 150 100 1 1000 120 70 1
0.75VDD 0.40VDD
Unit
mA A A A A A A A V V A A mA A A A V V V mA A A A A A A A K % %
Conditions
VDD=5.5V,no load,NORMAL mode, Fc=4MHz, Fs=32KHz (crystal) VDD=5.5V,no load,SLOW mode,Fs=32KHz (crystal) VDD=5.5V,no load,RVRLC=68K,IDLE mode, Fs=32KHz (crystal) VDD=5.5V,STOP mode (crystal) VDD=5.5V,no load,NORMAL mode, Fc=4MHz,Fs=32KHz (RC, OSC) VDD=5.5V,no load,SLOW mode,Fs=32KHz (RC, OSC) VDD=5.5V,no load,RVRLC=68K,IDLE mode, Fs=32KHz (RC, OSC) VDD=5.5V,STOP mode (RC, OSC) RESET,all I/O ports RESET,P0,VDD=5.5V,VIH=5.5/0V Open-drain,VDD=5.5V,VIH=5.5/0V P1,P2 P0, I/O port acts as input(push-pull), P4~P8, optional,VDD=4.5V,VIL=0.2V P11,P15 VDD=4.5V,see IOH=typical. for P4~P8,P11, P15,P30,P31 VDD=4.5V,IOL=0.5mA,P1,P2, P4,P7,P8, P11,P15,P17.0,P30,P31 VDD=4.5V,IOL=16mA,P5,P6 P1,P2 VDD=4.5V,VOH=2.2V
I DD_RC
Hysteresis voltage Input current
V HYS+ V HYSI IH
0.50VDD 0.20VDD
High current Normal current I IL
High current I IL1
Low current
Output Voltage
VOH V OL
11 450 50 20 2.2 9 45 18 400 45 16 45 -
1 1 18 650 80 28 0.2
High current
Normal current
I OH1
Low current
High current IOH Normal current
Low current
Normal current
Leakage current Input resistor High Frequency Variation Low Frequency Variation
ILO RIN
1.0 14 65 27 500 65 25 65 1 30 30
P4~P8, P11,P15,P30,P31, optional P17.0 Open-drain,VDD=5.5V,Vo=5.5V RESET VDD=2.2~5.5V+10% RC OSC R=100K+2%, fc=4MHz VDD=2.2~5.5V+10% RC OSC R=1M+2%, fs=32KHz 8.14.2001
43
Note : RESET pin must add to a pull-up resistor. * This specification are subject to be changed without notice.
inary Prelim
PAD DIAGRAM
SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
98
114 113 SEG42 SEG43 SEG44/P31.3 SEG45/P31.2 SEG46/P31.1 SEG47/P31.0 SEG48/P30.3 SEG49/P30.2 SEG50/P30.1 SEG51/P30.0 VPP/TEST ACLK/P0.0 PGM/P0.1 OE/P0.2 DCLK/P0.3 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 RESET P6.0 P6.1 P6.2 P6.3 P7.0 P7.1 P7.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
112
111
110 109 108
107 106
105
104 103
102
101 100 99
97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM4 COM3 COM2 COM1 COM0 P15.3 P15.2 P15.1 P15.0 P11.3 P11.2 P11.1 P11.0 VRLC VR3
(0,0)
76 75
EM73P968
74 73 72 71 70 69 68 67 66 65 64 63 62
ELAN
36 37 38 39 40 41
61 60 59 58 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
VADSS
VREF
VSS
VSS
VAD
P8.0/DIN
P8.1/DOUT
VDD
XOUT
LXIN
VDD
LXOUT
VR1
P7.3
P8.2
P8.3
XIN
* This specification are subject to be changed without notice.
VR2
SEG24
8.14.2001
44
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ary elimin Pr
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol SEG42 SEG43 SEG44/P31.3 SEG45/P31.2 SEG46/P31.1 SEG47/P31.0 SEG48/P30.3 SEG49/P30.2 SEG50/P30.1 SEG51/P30.0 VPP/TEST P0.0/ACLK P0.1/PGM P0.2/OE P0.3/DCLK P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 RESET P6.0 P6.1 P6.2 P6.3 P7.0 P7.1 P7.2 P7.3 X -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 -935.0 Y 2080.0 1960.0 1845.0 1730.0 1615.0 1505.0 1395.0 1285.0 1175.0 1065.0 955.0 847.5 740.0 632.5 525.0 420.0 315.0 210.0 105.0 0.0 -105.0 -210.0 -315.0 -420.0 -525.0 -632.5 -740.0 -847.5 -955.0 -1065.0 -1175.0 -1285.0 -1395.0 -1505.0 -1615.0 -1730.0 -1845.0 -1960.0 -2080.0 -2200.0
* This specification are subject to be changed without notice.
8.14.2001
45
inary Prelim
Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol VADSS VREF VAD P8.0/DIN P8.1/DOUT P8.2 P8.3 VSS XIN VDD XOUT VSS LXIN VDD LXOUT VR1 VR2 VR3 VRLC P11.0 P11.1 P11.2 P11.3 P15.0 P15.1 P15.2 P15.3 COM0 COM1 COM2 COM3 COM4 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
X -815.0 -700.0 -590.0 -480.0 -372.5 -265.0 -157.5 -52.5 52.5 157.5 265.0 372.5 480.0 590.0 700.0 815.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0
Y -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2200.0 -2080.0 -1960.0 -1845.0 -1730.0 -1615.0 -1505.0 -1395.0 -1285.0 -1175.0 -1065.0 -955.0 -847.5 -740.0 -632.5 -525.0 -420.0 -315.0 -210.0 -105.0 0.0 105.0 210.0 315.0
* This specification are subject to be changed without notice.
8.14.2001
46
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ary elimin Pr
Pad No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Symbol SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 X 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 935.0 815.0 700.0 590.0 480.0 372.5 265.0 157.5 52.5 -52.5 -157.5 -265.0 -372.5 -480.0 -590.0 -700.0 -815.0 -935.0 Y 420.0 525.0 632.5 740.0 847.5 955.0 1065.0 1175.0 1285.0 1395.0 1505.0 1615.0 1730.0 1845.0 1960.0 2080.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0 2200.0
Unit : um Chip size : 2130 x 4660um Note : For PCB layout, IC substrate must be floated or connected to Vss.
* This specification are subject to be changed without notice.
8.14.2001
47
PACKAGE DIMENSION
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
A
Symbol A A2 A1 b c D Hd E He L L1 e
Min 2.540 0.250
Normal 2.720 0.350 0.2(TYP) 0.15(TYP) 14.000 17.200 20.000 23.200 0.800 1.600 0.5(bsc)
Max 3.400 2.900 0.450
13.900 17.000 19.900 23.000 0.650 1.400 0
14.100 17.400 20.100 23.400 0.950 1.800 7
All dimensions are in millimeters.
* This specification are subject to be changed without notice.
8.14.2001
48
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INSTRUCTION TABLE
(1) Data Transfer Mnemonic
ary elimin Pr
Object code ( binary ) Operation description AccRAM[x] Acc RAM[HL] AccROM[DP] L AccROM[DP] H,DP+1 HRk LRRAM[x],HRRAM[x+1] Acck LRk RAM[x]Acc RAM[HL]Acc RAM[HL]Acc, LR-1 RAM[HL]Acc, LR+1 RAM[y]k RAM[HL]k, LR+1 AccHR AccLR
Byte 2 1 1 1 1 2 1 1 2 1 1 1 2 1 1 1
Cycle 2 1 2 2 1 2 1 1 2 1 1 1 2 1 1 1
LDA x 0110 1010 xxxx xxxx LDAM 0101 1010 LDAX 0110 0101 LDAXI 0110 0111 LDH #k 1001 kkkk LDHL x 0100 1110 xxxx xx00 LDIA #k 1101 kkkk LDL #k 1000 kkkk STA x 0110 1001 xxxx xxxx STAM 0101 1001 STAMD 0111 1101 STAMI 0111 1111 STD #k,y 0100 1000 kkkk yyyy STDMI #k 1010 kkkk THA 0111 0110 TLA 0111 0100 (2) Rotate Mnemonic RLCA RRCA
C -
Flag Z Z Z Z Z Z Z Z Z Z Z
S 1 1 1 1 1 1 1 1 1 1 C C' 1 C' 1 1
Object code ( binary ) Operation description 0101 0000 0101 0001 CFAcc CFAcc
Byte 1 1
Cycle 1 1
C C C
Flag Z Z Z
S C' C'
(3) Arithmetic operation Mnemonic ADCAM ADD #k,y ADDA #k ADDAM ADDH #k ADDL #k ADDM #k DECA DECL DECM INCA Object code ( binary ) Operation description 0111 0100 0110 0111 0110 0110 0110 0101 0111 0101 0101 0000 1001 kkkk yyyy 1110 0101 kkkk 0001 1110 1001 kkkk 1110 0001 kkkk 1110 1101 kkkk 1100 1100 1101 1110 AccAcc + RAM[HL] + CF RAM[y]RAM[y] + k AccAcc+k AccAcc + RAM[HL] HRHR+k LRLR+k RAM[HL]RAM[HL] +k AccAcc-1 LRLR-1 RAM[HL]RAM[HL] -1 AccAcc + 1 Byte 1 2 2 1 2 2 2 1 1 1 1 Cycle 1 2 2 1 2 2 2 1 1 1 1 C C Flag Z Z Z Z Z Z Z Z Z Z Z Z S C' C' C' C' C' C' C' C C C C'
* This specification are subject to be changed without notice.
8.14.2001
49
INCL INCM SUBA #k SBCAM SUBM #k
0111 1110 0101 1111 0110 1110 0111 kkkk 0111 0010 0110 1110 1111 kkkk
inary Prelim
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
LRLR + 1 RAM[HL]RAM[HL]+1 Acck-Acc AccRAM[HLl - Acc - CF' RAM[HL]k - RAM[HL]
1 1 2 1 2
1 1 2 1 2
C -
Z Z Z Z Z
C' C' C C C
(4) Logical operation
Mnemonic ANDA #k ANDAM ANDM #k ORA #k ORAM ORM #k XORAM (5) Exchange Mnemonic Object code (binary) Operation description Byte Cycle Flag C Z S Object code (binary) 0110 0111 0110 0110 0111 0110 0111 1110 0110 kkkk 1011 1110 1110 kkkk 1110 0100 kkkk 1000 1110 1100 kkkk 1001 Operation description AccAcc&k AccAcc & RAM[HL] RAM[HL]RAM[HL]&k AccAcc k Acc Acc RAM[HL] RAM[HL]RAM[HL] k AccAcc^RAM[HL]
-----
Byte 2 1 2 2 1 2 1
Cycle 2 1 2 2 1 2 1
C -
Flag Z Z Z Z Z Z Z Z
S Z' Z' Z' Z' Z' Z' Z'
EXA x EXAH EXAL EXAM EXHL x (6) Branch
Mnemonic
0110 1000 xxxx xxxx 0110 0110 0110 0100 0101 1000 0100 1100 xxxx xx00
AccRAM[x] AccHR AccLR AccRAM[HL] LRRAM[x], HRRAM[x+1]
2 1 1 1 2
2 2 2 1 2
-
Z Z Z Z -
1 1 1 1
-
1
Object code (binary)
Operation description
Byte
Cycle
SBR a LBR a SLBR a
00aa aaaa 1100 aaaa aaaa aaaa 0101 0101 1100 aaaa 0101 0111 1100 aaaa
aaaa aaaa (a:1000~1FFFh) aaaa aaaa (a:0000~0FFFh)
If SF=1 then PCPC12-6.a5-0 elsenull If SF= 1 then PCa else null If SF=1 then PCa else null
1 2 3
1 2 3
Flag C Z
-
-
S
1 1 1
-
-
(7) Compare
Mnemonic Object code (binary) Operation description Byte Cycle Flag C Z S
CMP #k,y 0100 1011 kkkk yyyy CMPA x 0110 1011 xxxx xxxx
k-RAM[y] RAM[x]-Acc
2 2
2 2
C C
Z Z
Z' Z'
50
* This specification are subject to be changed without notice.
8.14.2001
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Mnemonic
Object code ( binary )
ary elimin Pr
RAM[HL] - Acc k - HR k - Acc k-LR
Operation description
Byte
Cycle
CMPAM CMPH #k CMPIA #k CMPL #k
0111 0011 0110 1110 1011 kkkk 1011 kkkk 0110 1110 0011 kkkk
1 2 1 2
1 2 1 2
C C -
C
Flag Z
Z Z Z Z
Z' C Z' C
S
(8) Bit manipulation Mnemonic CLM CLP CLPL CLR SEM SEP SEPL SET TF TFA TFM TFP TFPL TT TTP b p,b y,b b p,b y,b y,b b b p,b y,b p,b Object code ( binary ) 1111 00bb 0110 1101 11bb pppp 0110 0000 0110 1100 11bb yyyy 1111 01bb 0110 1101 01bb pppp 0110 0010 0110 1100 01bb yyyy 0110 1100 00bb yyyy 1111 10bb 1111 11bb 0110 1101 00bb pppp 0110 0001 0110 1100 10bb yyyy 0110 1101 10bb pppp Operation description RAM[HL]b0 PORT[p]b0 PORT[LR3-2+4]LR1-00 RAM[y]b0 RAM[HL]b1 PORT[p]b1 PORT[LR3-2+4]LRl-01 RAM[y]b1 SFRAM[y]b' SFAcc b' SFRAM[HL]b' SFPORT[p]b' SFPORT[LR 3-2 +4]LR1-0' SFRAM[y]b SFPORT[p]b Byte 1 2 1 2 1 2 1 2 2 1 1 2 1 2 2 Cycle 1 2 2 2 1 2 2 2 2 1 1 2 2 2 2 C Flag Z S 1 1 1 1 1 1 1 1 * * * * * * *
(9) Subroutine Mnemonic LCALL a SCALL a RET (10) Input/output Mnemonic INA INM OUT OUTA OUTM p p #k,p p p Object code ( binary ) 0110 1111 0100 pppp 0110 1111 1100 pppp 0100 1010 kkkk pppp 0110 1111 000p pppp 0110 1111 100p pppp Operation description AccPORT[p] RAM[HL]PORT[p] PORT[p]k PORT[p]Acc PORT[p]RAM[HL] Byte 2 2 2 2 2 Cycle 2 2 2 2 2 C Flag Z Z S Z' Z' 1 1 1
51
Object code ( binary ) 0100 0aaa aaaa aaaa 1110 nnnn 0100 1111
Operation description STACK[SP]PC, SPSP -1, PCa STACK[SP]PC, SPSP - 1, PCa, a = 8n + 6 (n =115),0086h (n = 0) SPSP + 1, PCSTACK[SP]
Byte 2 1 1
Cycle 2 2 2
C -
Flag Z -
S -
* This specification are subject to be changed without notice.
8.14.2001
(11) Flag manipulation Mnemonic TFCFC TTCFS TZS Object code ( binary ) 0101 0011 0101 0010 0101 1011
inary Prelim
SFCF', CF0 SFCF, CF1 SFZF
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Operation description
Byte 1 1 1
Cycle 1 1 1
C 0 1 -
Flag Z -
S * * *
(12) Interrupt control Mnemonic CIL r DICIL r EICIL r EXAE RTI (13) CPU control Mnemonic NOP Object code ( binary ) 0101 0110 Operation description no operation Byte 1 Cycle 1 C Flag Z S Object code ( binary ) 0110 0011 11rr rrrr 0110 0011 10rr rrrr 0110 0011 01rr rrrr 0111 0101 0100 1101 Operation description ILIL & r EIF0,ILIL&r EIF1,ILIL&r MASKAcc SPSP+1,FLAG.PC STACK[SP],EIF 1 Byte 2 2 2 1 1 Cycle 2 2 2 1 2 C * Flag Z * S 1 1 1 1 *
(14) Timer/Counter & Data pointer & Stack pointer control Mnemonic LDADPL LDADPM LDADPH LDASP LDATAL LDATAM LDATAH LDATBL LDATBM LDATBH STADPL STADPM STADPH STASP STATAL STATAM STATAH STATBL STATBM STATBH Object code ( binary ) 0110 1010 1111 1100 0110 1010 1111 1101 0110 1010 1111 1110 0110 1010 1111 1111 0110 1010 1111 0100 0110 1010 1111 0101 0110 1010 1111 0110 0110 1010 1111 1000 0110 1010 1111 1001 0110 1010 1111 1010 0110 1001 1111 1100 0110 1001 1111 1101 0110 1001 1111 1110 0110 1001 1111 1111 0110 1001 1111 0100 0110 1001 1111 0101 0110 1001 1111 0110 0110 1001 1111 1000 0110 1001 1111 1001 0110 1001 1111 1010 Operation description Acc[DP] L Acc[DP] M Acc[DP] H AccSP Acc[TA] L Acc[TA]M Acc[TA] H Acc[TB] L Acc[TB]M Acc[TB]H [DP] L Acc [DP] M Acc [DP] HAcc SPAcc [TA] LAcc [TA] MAcc [TA] HAcc [ TB] LAcc [TB] MAcc [TB] HAcc Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C Flag Z Z Z Z Z Z Z Z Z Z Z S 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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* This specification are subject to be changed without notice.
8.14.2001
EM73P968 4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
**** SYMBOL DESCRIPTION
Symbol HR PC SP ACC CF SF IL PORT[p] RAM[x] ROM[DP]H [DP]M [TA]L([TB]L) [TA]H([TB]H) LR3-2 PC12-6 --
ary elimin Pr
Symbol LR DP STACK[SP] FLAG ZF EI MASK RAM[HL] ROM[DP]L [DP]L [DP]H [TA]M([TB]M) LR 1-0 a5-0 + & ^ . x p r Description L register Data pointer Stack specified by SP All flags Zero flag Enable interrupt register Interrupt mask Timer/counter A Data memory (address : HL ) Low 4-bit of program memory Low 4-bit of data pointer register High 4-bit of data pointer register Middle 4-bit of timer/counter A (timer/counter B) register Contents of bit assigned by bit 1 to 0 of LR Bit 5 to 0 of destination address for branch instruction Transfer Addition Logic AND Logic XOR Concatenation 8-bit RAM address 4-bit or 5-bit port address 6-bit interrupt latch
Description H register Program counter Stack pointer Accumulator Carry flag Status flag Interrupt latch Port ( address : p ) Timer/counter B Data memory (address : x ) High 4-bit of program memory Middle 4-bit of data pointer register Low 4-bit of timer/counter A (timer/counter B) register High 4-bit of timer/counter A (timer/counter B) register Bit 3 to 2 of LR Bit 12 to 6 of program counter Exchange Substraction Logic OR Inverse operation 4-bit immediate data 4-bit zero-page address Bit address
#k y b
* This specification are subject to be changed without notice.
8.14.2001
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